CRAC Class C (2025) — Questions 1131–1140
Unofficial study reference only. Not affiliated with the FCC, NCVEC or CRAC — official sources prevail. 非官方学习参考，与 FCC、NCVEC、CRAC 无隶属关系；以官方发布为准。
U1300. The two-input OR gate is one of the simplest digital logic circuits. If the two inputs are respectively 00, 01, 10, 11, the corresponding outputs are:
具有两个输入端的或门（OR）是最简单的数字逻辑电路之一。 如果这两个输入的组合分别为00、01、10、11，则对应的输 出为：
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An OR gate outputs 1 if either input is 1: 00→0, 01→1, 10→1, 11→1, i.e. 0,1,1,1 (A). B is NOR-like, C is XOR, D is a non- standard pattern.
U1301. The two-input XOR (exclusive-OR) gate is one of the simplest digital logic circuits. If the two inputs are respectively 00, 01, 10, 11, the corresponding outputs are:
具有两个输入端的异或门（XOR）是最简单的数字逻辑电路之 一。如果这两个输入的组合分别为00、01、10、11，则对应 的输出为：
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An XOR gate outputs 1 when the inputs differ: 00→0, 01→1, 10→1, 11→0, i.e. 0,1,1,0 (A). B is XNOR, C is OR, D is non- standard.
U1302. The two-input NAND (NOT-AND) gate is one of the simplest digital logic circuits. If the two inputs are respectively 00, 01, 10, 11, the corresponding outputs are:
具有两个输入端的与非门（NAND）是最简单的数字逻辑电路 之一。如果这两个输入的组合分别为00、01、10、11，则对 应的输出为：
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A NAND gate is the inversion of AND: 00→1, 01→1, 10→1, 11→0, i.e. 1,1,1,0 (A). B is OR, C is XOR, D is non-standard.
U1303. The two-input NOR (NOT-OR) gate is one of the simplest digital logic circuits. If the two inputs are respectively 00, 01, 10, 11, the corresponding outputs are:
具有两个输入端的或非门（NOR）是最简单的数字逻辑电路之 一。如果这两个输入的组合分别为00、01、10、11，则对应 的输出为：
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A NOR gate is the inversion of OR: 00→1, 01→0, 10→0, 11→0, i.e. 1,0,0,0 (A). B is OR, C is XOR, D is non-standard.
U1304. The two-input XNOR (exclusive-NOR / equivalence) gate is one of the simplest digital logic circuits. If the two inputs are respectively 00, 01, 10, 11, the corresponding outputs are:
具有两个输入端的异或非门（NXOR）是最简单的数字逻辑电 路之一。如果这两个输入的组合分别为00、01、10、11，则 对应的输出为：
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An XNOR (equivalence) gate outputs 1 when inputs are equal: 00→1, 01→0, 10→0, 11→1, i.e. 1,0,0,1 (A). B is OR, C/D are non- standard.
U1305. A
D触发器是一种时序逻辑电路，具有数据输入端D、时钟输入端 CK和数据输出端Q。假设D触发器由CK的上升沿触发，则其工 作情况为：
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A rising-edge-triggered D flip-flop copies D to Q on each rising clock edge (A). B would be a D with inversion (not a plain D); C/D describe falling-edge behavior, which contradicts the stated rising-edge trigger.
U1306. A
D触发器是一种时序逻辑电路，具有数据输入端D、时钟输入端 CK和数据输出端Q。若将D触发器的Q端反相之后连到D端，则 在每次CK上升沿到来时会发生什么？
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Feeding /Q back to D makes the flip-flop toggle every clock edge, so Q changes once per full CK period — a divide-by-2 (A). It cannot multiply frequency (B); the output is a 50% square wave at f/2, not a fixed 90°/180° phase of CK (C/D).
U1307. When building SDR (software-defined radio) projects, especially direct-RF-sampling digital transceivers, we use a field-programmable logic device called an FPGA. In an SDR system, an FPGA can be used to: (Choose all that apply.)
制作SDR作品，特别是在制作直接射频采样的数字收发信机 时，我们会使用一种叫做FPGA的现场可编程数字逻辑器件。 FPGA在SDR系统中可以用来：
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An FPGA provides reconfigurable parallel hardware: it does the DSP (mixing, filtering, decimation/rate conversion) (A), can embed a soft-CPU to run the SDR (B), and offloads parallel work from a host PC (C). D (acting as storage/SSD) is not an FPGA function, so it is not selected.
U1308. The first step of digital signal processing (DSP) is converting the analog signal to a digital signal. To ensure the frequency components of the analog signal do not alias in the captured samples, the sampling rate of the analog-to-digital converter (ADC) must be higher than:
实现数字信号处理（DSP）的第一步是将模拟信号转换为数字 信号。为确保模拟信号的各频率成分不会在采集的样本中发生 混叠，模数转换器（ADC）的采样率必须高于：
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This is the Nyquist–Shannon sampling theorem: to avoid aliasing, the ADC sample rate must exceed 2× the highest input frequency (A). B/C/D are unrelated quantities.
U1309. The first step of digital signal processing (DSP) is converting the analog signal to a digital signal. The quantization precision of the analog-to-digital converter (ADC) used depends on:
实现数字信号处理 (DSP) 的第一步是将模拟信号转换为数字信 号。所用模数转换器（ADC）的量化精度取决于：
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Quantization precision (the ADC's bit depth) sets the amplitude resolution; the required precision is governed by the signal's dynamic range / waveform complexity (how finely you must resolve amplitude detail), so A is marked. Note that the ADC's inherent resolution is a fixed hardware property, while B (2× highest frequency) is the separate Nyquist sampling-rate requirement, not quantization precision.